In a semiconductor memory device, memory cells may be susceptible to single-bit errors based on a transient error or a soft error. The single-bit error may be due to a transient error caused by noises from surrounding components in the device with high-density. A soft error may be caused by background radiation. Memories have been developed that include error detection and/or error correcting codes (ECC) to correct these single-bit errors. The error detection and ECC are typically a simple parity check error detection or a relatively simple single-error-correcting (SEC) Hamming code, a single-error-correcting-double-error-detecting (SEC-DED) extended-Hamming code, etc. For high-precision systems that require high reliability, such as network applications, any critical error which causes the system to operate incorrectly is not acceptable and these simple ECC codes may not be sufficient. Thus, these high-precision systems tend to utilize more complex codes which are capable of correcting multiple bits, such as a double-error-correcting-triple-error-detecting (DEC-TED) Bose-Chaudhuri-Hocquenghem (BCH) code and a Reed-Solomon code. However, the complexity of these codes having more check bits may result in increased die size and longer processing time, neither of which may be desirable in high-speed and compact memory applications.
In recent years, there has been an effort to correct memory bit errors while maintaining higher data transfer rates and reducing die sizes. For example, U.S. patent application publication 2014/0189468 A1 describes memory devices including control circuitry which is able to adjust a size of one or more of the ECC coverage areas. Another example is U.S. patent application publication 2015/0074493 A1, which describes a semiconductor device including a reduced number of reference cells for error detection and correction.